Typical multi-core processors need to manage cache and cache coherency for each of the processing cores. Cache coherency is often managed by using a plurality of caches and tying each cache to a particular processing core. In other systems, a shared cache is used. In typical multi-core processors with a shared cache, access to the shared cache is arbitrated. These methods may be effective for applications in which the executed code and data sets are independent for each processor core. However, for applications in which the code space (e.g. operating system, I/O routines, algorithms, etc.) is common and/or the data set is shared, independent caches requires cache coherency algorithms that can significantly reduce bandwidth and make the cache areas ineffective since redundant information is stored in multiple caches. In addition, when a single cache is arbitrated between multiple processor cores, the bandwidth to the cache for a given processor core is reduced by the actions of the other processor cores.